Sr. Principal Architect: On-Die Interconnect at Ampere Computing
Santa Clara, CA 95050
About the Job
DescriptionInvent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply! About the role: We are looking for an experienced coherent interconnect architect for our future AI accelerator product roadmap.
This is an exciting opportunity to be at the forefront of new architecture developments in this strategically critical project.
In this role you will join our mesh architecture team to define enhancements and new sub-components for our custom interconnect IP, to meet the requirements of the product.
You will be responsible for defining the topology and routing algorithms of the product for both mainband and sideband fabrics.
You will also work with, mentor, and support the architects responsible for die-to-die and chip-to-chip links to ensure that the entire interconnect network delivers the necessary performance across the system.What you’ll achieve: Own the architecture of the product interconnect from initial path-finding to production and support it through execution to product tape-out; and through post-si validation to productionWork with the broader AI accelerator team to understand the target workloads and compute and memory needs of the product and translate this into requirements of the interconnectBalance features, performance, power, and area to create a solution; with high value and optimal use of development and physical resourcesWork with the performance modeling team to evaluate critical metrics such as bandwidth and latency to ensure the interconnect is optimized for the target workloadsEnsure that the on-die interconnect works seamlessly with the die-to-die and chip-to-chip interfaces, for efficient inter-die and inter-package communicationUse data-based analysis to study trade-offs that include protocol efficiency, bandwidth, and latency to inform or make critical product and IP decisionsCreate and maintain clear, detailed, and comprehensive product architecture specs, including performance targetsCreate and maintain configuration and programming guides as a reference for design integration and FW teamsWork with the existing mesh team to define and drive enhancements, additions, and other updates to our existing custom AMBA-based interconnects to meet the needs of the product; write and update IP-level architecture specs to define these changes and work with the engineering team to ensure they are implemented as definedHelp to define the cache hierarchy of the product, including any enhancements to the HW coherency protocol, to optimize the overall product based on workload analysis and by understanding the rest of the product architectureEvaluate network topology and routing options to optimize for efficient data movement while ensuring the network is deadlock freeDefine QoS, RAS, and debug requirements for the on-die interconnectsDrive performance correlation of models using post-silicon measurement data or pre-silicon simulation resultsHelp to define design (DV) and performance (PV) verification plansAbout you: BS degree in Electrical Engineering, Computer Engineering, or Computer Science and 12 years of experience; or MS degree and 8 years of experience; or PhD degree and 5 years of experienceExperience architecting and/or designing high-performance, high-bandwidth on-die coherent interconnects (mesh, NoC, fabric, etc.) Deep understanding of cache-coherency protocols is a must-have; AMBA CHI would be a plusUnderstanding of ordering, in-out dependencies, and deadlocksExperience with cache architecture and/or design (preferred)Experience with chiplet-based SoC architecture, including advanced package technologies and die-to-die interface technologies and trade-offs (preferred)Experience with AI accelerator or GPU architectures (preferred)Knowledge and understanding of AMBA suite of interface protocols (preferred)Knowledge and understanding of PCIe and CXL (preferred)Must be self-driven, curious, organized and comfortable with ambiguityAbility to learn and adapt, one of the foundational principles of AmpereGreat communication skills, comfortable with reaching out and asking questions, and brainstorming with peers – working at Ampere is very much a team sport!What we’ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits.
The full base pay range for this role is between $163,100 and $271,900, except in the San Francisco Bay Area where the range is between $171,800 and $286,300.
We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company. Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.
Benefits highlights include: Premium medical, dental, vision insurance, as well as income protection and a 401K retirement plan, so thatyou can feel secure in your health and financial future Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day And there is much more than compensation and benefits.
At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future.
We are excited to share more about our career opportunities with you through the interview process. #LI-CB1 #LI-HybridAmpere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds.
All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.
This is an exciting opportunity to be at the forefront of new architecture developments in this strategically critical project.
In this role you will join our mesh architecture team to define enhancements and new sub-components for our custom interconnect IP, to meet the requirements of the product.
You will be responsible for defining the topology and routing algorithms of the product for both mainband and sideband fabrics.
You will also work with, mentor, and support the architects responsible for die-to-die and chip-to-chip links to ensure that the entire interconnect network delivers the necessary performance across the system.What you’ll achieve: Own the architecture of the product interconnect from initial path-finding to production and support it through execution to product tape-out; and through post-si validation to productionWork with the broader AI accelerator team to understand the target workloads and compute and memory needs of the product and translate this into requirements of the interconnectBalance features, performance, power, and area to create a solution; with high value and optimal use of development and physical resourcesWork with the performance modeling team to evaluate critical metrics such as bandwidth and latency to ensure the interconnect is optimized for the target workloadsEnsure that the on-die interconnect works seamlessly with the die-to-die and chip-to-chip interfaces, for efficient inter-die and inter-package communicationUse data-based analysis to study trade-offs that include protocol efficiency, bandwidth, and latency to inform or make critical product and IP decisionsCreate and maintain clear, detailed, and comprehensive product architecture specs, including performance targetsCreate and maintain configuration and programming guides as a reference for design integration and FW teamsWork with the existing mesh team to define and drive enhancements, additions, and other updates to our existing custom AMBA-based interconnects to meet the needs of the product; write and update IP-level architecture specs to define these changes and work with the engineering team to ensure they are implemented as definedHelp to define the cache hierarchy of the product, including any enhancements to the HW coherency protocol, to optimize the overall product based on workload analysis and by understanding the rest of the product architectureEvaluate network topology and routing options to optimize for efficient data movement while ensuring the network is deadlock freeDefine QoS, RAS, and debug requirements for the on-die interconnectsDrive performance correlation of models using post-silicon measurement data or pre-silicon simulation resultsHelp to define design (DV) and performance (PV) verification plansAbout you: BS degree in Electrical Engineering, Computer Engineering, or Computer Science and 12 years of experience; or MS degree and 8 years of experience; or PhD degree and 5 years of experienceExperience architecting and/or designing high-performance, high-bandwidth on-die coherent interconnects (mesh, NoC, fabric, etc.) Deep understanding of cache-coherency protocols is a must-have; AMBA CHI would be a plusUnderstanding of ordering, in-out dependencies, and deadlocksExperience with cache architecture and/or design (preferred)Experience with chiplet-based SoC architecture, including advanced package technologies and die-to-die interface technologies and trade-offs (preferred)Experience with AI accelerator or GPU architectures (preferred)Knowledge and understanding of AMBA suite of interface protocols (preferred)Knowledge and understanding of PCIe and CXL (preferred)Must be self-driven, curious, organized and comfortable with ambiguityAbility to learn and adapt, one of the foundational principles of AmpereGreat communication skills, comfortable with reaching out and asking questions, and brainstorming with peers – working at Ampere is very much a team sport!What we’ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits.
The full base pay range for this role is between $163,100 and $271,900, except in the San Francisco Bay Area where the range is between $171,800 and $286,300.
We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company. Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.
Benefits highlights include: Premium medical, dental, vision insurance, as well as income protection and a 401K retirement plan, so thatyou can feel secure in your health and financial future Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day And there is much more than compensation and benefits.
At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future.
We are excited to share more about our career opportunities with you through the interview process. #LI-CB1 #LI-HybridAmpere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds.
All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.