Silicon Operation Engineering Manager - Google
Sunnyvale, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 10 years of experience in IC product development or test engineering, and manufacturing (i.e., characterization, qualification, bring-up, yield improvement, and debug).
- Experience building test program and HVM floor engineering support/management.
- Experience working with vendors.
Preferred qualifications:
- Experience in wafer probe card, ATE hardware, and managing suppliers on execution of test hardware development and bring-up.
- Experience in test engineering, DFT, test hardware, and test program development (e.g., Teradyne UltraFlex, Advantest 93k platforms).
- Experience in programming/scripting (e.g., C and C++, Python, or Perl).
- Knowledge of probability and statistical fundamentals for data analysis and process control design.
About the job
As a Silicon Operation Engineering Manager, you will build High Quality Test programs and take it to HVM (High Volume Manufacturing). You will define, lead, and track our products operation covering HVM, NPI, ATE Test and Characterization, System level Testing, Yield improvements processes. You will deliver products in the fabless semiconductor model with deep knowledge covering the full manufacturing flow including High volume production, fab, test, DFT, package assembly, and qualification.
In this role, you will be managing a team that is responsible for developing test programs and hardware for wafer probe and the ATE (Automated Testing Equipment) for characterization and production testing of very high performance networking and machine learning ICs. You will need to be able to utilize the ATE equipment tools and capabilities to optimize final test programs without compromising the quality of outgoing products. You will also be responsible for developing test plans and supporting the full life cycle of the product from design to volume manufacturing.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Be responsible for Silicon product Engineering Activities including New Product Introduction (NPI), System Level testing, and HVM (including Yields analysis and Return Merchandise Authorization (RMA)/Failure Analysis (FA)).
- Lead a team to develop silicon product test hardware and software, silicon data analytics, and system level testing.
- Build up HVM test engineering supply chain with the necessary tracking, managing, and Yield/Quality correlation analysis to optimize cost.
- Develop a robust NPI team across all regions to facilitate the execution of multiple products. Prioritize the creation of a systematic NPI Test Program strategy that includes clear definition, efficient execution, and ongoing refinement.
- Build and track high performance IC test and characterization flows for PVT, signal and power integrity characterization, and participate in silicon debug, Electrical Failure Analysis (EFA), and Physical Failure Analysis (PFA).