Silicon Design Lead, Devices and Services - Google
Mountain View, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- 4 years of experience in people management, leading IP/SoC design team for low power SoCs.
- Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical/Computer Engineering, or a related field.
- 15 years of experience with IP design for clocking, interconnects, and peripherals.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience managing technical teams.
- Ability to drive multi-generational roadmap for IP/SoC development.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.
As a Silicon Design Lead, you will be part of the team that designs chassis IPs (NoC, Clock, Debug, QoS, etc.) and subsystems for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality RTL design. You'll solve technical problems with innovative micro-architecture, low power design methodology, and evaluate design options with complexity, performance, power, and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Lead a team that delivers fabric interconnect IP, sub-system.
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Oversee RTL development, debug functional/performance simulations.
- Meet schedule commitments and provide strong support to customers.
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.