Senior Staff Physical Design Engineer - Google
Sunnyvale, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years experience in ASIC physical design flows and methodologies in advanced process nodes.
- Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools).
- Scripting experience with Python, Tcl, or Perl.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience leading one or more aspects of physical design and working with IP integration (memories, IO’s and Analog IP).
- Experience solving physical design challenges across various technologies (e.g., embedded processors, DDR, networking fabrics, etc.).
- Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation.
- Knowledge of semiconductor device physics, transistor characteristics, and SystemVerilog/Verilog.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Lead the effort for timing closure of blocks, subsystems, and fullchip.
- Drive physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or fullchip.
- Work with logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.
- Drive physical design methodologies and automation scripts for various implementation steps.
- Perform technical evaluations of vendors, process nodes, IP, and provide recommendations.
Source : Google