Senior Power & Performance Engineer - Microsoft Corporation

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Cloud Computer Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a **Senior Power and Performance Engineer** to join the team. **Responsibilities** + Work with business, architecture, and design teams to understand power and performance requirements and collaborate across functional teams to meet these needs in technology development planning and path finding. + Work with platform, firmware, and software teams across Microsoft to identify opportunities to improve system power and performance management with a goal of improved power efficiency across the stack. + Develop power and performance modeling methodology by creating and owning System on Chip (SOC) architectural power models. + Project and report power constrained SOC performance results to senior management. + Maintain the power modeling infrastructure, used for power constrained performance projections. + Work with IP Micro-architects and RTL team to incorporate low power design methodologies and power saving techniques. Identify IP/SOC power saving opportunities and drive definition of power saving uArch features. + Understand product SOC power and performance interactions with power delivery and thermal solutions at the system level. + Use case profiling, cloud computing workload analysis and PnP modeling, and correlation/validation to post-silicon. + Apply your growth mindset to learn and adapt in a complex and dynamic environment. **Qualifications** **Required/Minimum Qualifications** + 7+ years of related technical engineering experience + OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience + OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience + OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. + 4+ years of experience in SOC power architectural trade-off analysis or design **Other Qualifications:** + Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. **Additional or Preferred Qualifications** + Deep understanding of computer architecture, SOC and system-SW architectures, and their power/performance tradeoffs. + Experience developing SOC power and performance modeling techniques and benchmarks from conception to microarchitecture specification to post-silicon validation. + Understanding of memory and interconnect sub-systems. + Experience in development of analysis tools written in C++ and Python. + Knowledge of performance monitors and post-silicon SOC power and performance tuning. + Familiarity with ASIC power analysis, low power design and power optimization. + Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay Microsoft will accept applications for the role until January 9th, 2025. \#SCHIE #AHSI Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .