Semiconductor Design Engineer - Teradyne

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne (https://www.teradyne.com/) companies deliver manufacturing automation across industries and applications around the world!




Organization & Role



Teradyne’s Semiconductor Test Division in Agoura Hills, CA is looking for an enthusiastic candidate for the position of Semiconductor Design Engineer, to design high-speed analog circuits in mixed-signal ASICs for ATE (Automatic Test Equipment) instruments. We are looking for a candidate with CMOS design, modeling, and layout experience who has successfully taped-out several designs





Responsibilities




+ Develop detailed circuit specifications for mixed-signal circuits.


+ Design circuit architectures and transistor-level topologies to meet performance requirements.


+ Provide guidance for physical implementation (layout) of high-speed circuits.


+ Optimize circuits via simulation (using Cadence EDA tools) across various process and operating conditions.


+ Create cell / libraries models to be used for high level integrated functional and timing verification.


+ Integrate circuit elements into large analog/mixed-signal ASICs.


+ Participate in the characterization and testing of ASICs.






Basic Qualifications & Skills




+ Involved in all phases of multiple IC developments, from specification to product introduction.


+ Thorough knowledge of high-frequency, broad-band Analog Mixed-Signal IC design, covering both electrical and physical aspects.


+ Expertise in chip top-level logic and physical design, specializing in timing-aware logical partitioning, floor planning, and fast timing closure for mixed-signal chips.


+ Proficient in analog and mixed-signal modeling and verification for complex ICs, emphasizing functional and timing models as well as physical abstraction generation.


+ Solid understanding of Cadence RTL/STA/SDF gate-level verification flows.


+ Experience with standard and custom cell/IP cell library build, characterization, quality assurance, and release processes.


+ Collaborated extensively with EDA vendors to enhance tools and design flows, including Hard IP integration methodology.


+ Skilled in IC characterization at high frequency circuits, using tools such as high-speed sampling oscilloscopes, spectrum analyzers, VNAs, and signal sources.


+ Desired experience in CMOS FinFET (16nm or lower) design.


+ Verilog or Verilog-A modeling proficiency is a plus.






Education




+ MSEE or higher in electrical engineering with 15+ years of experience in designing and characterizing high-frequency, highly integrated mixed-signal integrated circuits.



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Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at HR.Service.Center@teradyne.com for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.