Principal Engineer/Manager, ASIC Digital Design - InnoPhase
San Jose, CA
About the Job
About InnoPhase, Inc.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about InnoPhase, check out InnoPhase's ceritification profile at GreatPlacetoWork.com and our website at www.innophaseinc.com.
As a Principal Engineer/Technical Lead, ASIC Digital Design, you will be leading with a small team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. You will support other discipline teams to bring the SoC device to successful mass production.
This full-time position is based in San Jose, CA.
Key Responsibilities
- Review and contribute to SoC system architecture and product specifications
- Technical leadership supporting team resource planning, project scheduling and tracking
- Perform all aspects of complex SoC design flow from micro-architecture definitions, CPU/bus/memory sub-system design, IP integration, and verification through physical implementation
- Work with IP/Design Verification/Firmware/Software System/Production teams to provide necessary support for timely closure of SoC design and implementation issues
Job Requirements
- MS/Ph.D. in EE or equivalent and 20 or more years of experience in SoC development and mass production
- Knowledge of ARM/RISC Architectures, Multi-core CPU operation and system memory partition/hierarchy
- Experience with AMBA AXI/AHB/APB Protocol bus architecture specification and implementation
- Thorough knowledge of Verilog/VHDL/System Verilog languages and front-end tools such as simulation, linting, clock-domain crossing checking, formal verification
- Proven knowledge of constraint definition, synthesis, static timing analysis and complete Front to Back SoC design/implementation flow
- Understanding of SCAN ATPG, BIST, DFT/DFM and fault coverage analysis
- Proven knowledge of System Verilog/UVM methodology and other advanced design verification techniques
- Proficiency of programming/scripting languages such as C/C++, Perl, Tcl, and Python
- Great collaborator and team player with effective communication/presentation skills and aggressive schedule/quality result driven mentality
Compensation and Benefits:
At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.