Principal Circuit Design Engineer - Microsoft

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsofts over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. 

 As Microsofts cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Circuit Design Engineer to design and build customer-focused solutions, discover insights and utilize industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.   

Qualifications

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 6+ years of experience in SRAM OR Register file design 

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications: 

• Understanding of SRAM write and read assist techniques 
• Deep understanding of industry trends in process and system-level technology 
• Expertise in yield and reliability 
• Experience in providing technical guidance to other engineers and multitasking across multiple SoC programs 
• Ability to concisely communicate design value propositions and risks 
• Excellent debug skills 
• 6+ years of experience in timing, power, EMIR characterization

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.

Microsoft will accept applications for the role until December 2, 2024.

Responsibilities

• Collaborate with SoC designers to develop Memory SRAM and Register file solutions to difficult PPA challenges 
• Work with internal and external process technology teams to understand and exploit advanced process DTCO knobs 
• Serve as technical lead to a team of circuit and mask layout engineers 
• Devise methodologies for statistical analysis and timing/power/EMIR characterization 
• Work alongside IP and SoC program management to develop milestone schedules and ensure proper delivery 
• Direct IP collateral quality assurance checking 
• Develop IP and post-silicon characterization plans for inclusion on advanced process technology testchips 
• Develop scripting automation for flows 
• Embody our Culture and Values