Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge.  We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform data-centre and AI ecosystems.

As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking technology. If you're ready to be a part of this journey, then we want to hear from you.

Intel's Xeon and Network engineering Group ( XNE) is a communications integrated circuit development team which create hardware assisted multi-core network processing, communication processors and customs integrated circuit solutions designed for use in wireline and wireless connectivity equipment. Our products integrate processors, network interfaces, signal processing components, packet processing, and security processors.

As part of XNE, your overall responsibilities will be to develop pre-silicon verification environments to test the complex functions in the SOC. The SOC Verification Engineer will:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
• Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Additional responsibilities include, but are not limited to:

• Working as part of team to define and document testbench architectures, models, tools, test plans and tests.
• Using System Verilog and UVM, implement reusable test bench components for blocks, subsystems, and the SOC.
• Developing and analyzing functional and code coverage to support the verification effort.
• Using formal property verification techniques to enhance cover quality.
• Utilizing functional and code coverage methodologies to ensure device quality.
• Working with team members to debug and resolve complex design and verification challenges.

The ideal candidate should exhibit the following behavioral traits:

• Excellent problem-solving and interpersonal skills, as well is good written and verbal communication skills.
• Willingness to work cross-geo/site when needed to accomplish results.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see(Minimum Qualifications):

• Candidate must have Bachelor's degree or Master's degree in Computer Engineering or Electrical Engineering.
• 7+ years experience digital verification methodologies using Verilog, System Verilog, UVM, and Formal (FPV) tools.
• 4+ years experience Linux based development verification flows and automation using scripting concepts.
• 3+ years' experience with data networking concepts such PCIE, Ethernet, 5G. etc.

How to Stand out (Preferred Qualifications):

• Working knowledge of Digital Signal Processing techniques.
• Experience with RF designs and complexities associated with validation mixed signal IP

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.  Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Pennsylvania, Allentown

Additional Locations:

US, Texas, Austin

Business group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.