PMTS, Integrated Circuit Digital Design Lead with Verification Experience - Integense

Integense is disrupting the semiconductor supply chain with innovative ASIC solutions. As an established provider of integrated circuit solutions for the industrial, solar, and energy storage markets, Integense is delivering world-class performance, superior cost structures, and high-volume manufacturing. We add value for our customers by applying a holisitic system-level approach combined with creative circuit design, proprietary silicon process technology and materials engineering, to provide optimal product solutions. We have been successful because we are nimble, innovative, and passionate about providing smarter solutions to our customers.

Our Automatic Test Equipment (ATE) group is expanding, and we are looking for a digital RTL designer with functional verification experience to lead our digital developments. In this role, you will work on developing the next generation of high-performance mixed-signal integrated circuits for tester applications.

As a senior digital design leader, you will be involved in all aspects of IC development, from product concept to manufacturing release. You will work with a cross-functional team of product definers, analog, and mixed-signal circuit designers to develop and verify digital designs for best in class ATE products.

Responsibilities:

• Complete Ownership of the Digital Design and Verification for ATE products - full Front End and Back End responsibility
• Define digital architecture and block-level requirements in collaboration with systems engineers and circuit designers
• Lead digital design and verification activities hands-on
• Work with EDA to develop design automation tools/scripts as needed
• Guide test engineering team to ensure robust production testing

Minimum requirements:

• MSEE electrical engineering
• 10+ years of Digital design experience in a Mixed Signal environment
• Full life-cycle experience demonstrated by multiple products in mass production
• Adept in front-end chip architecture and pre-silicon design flow, RTL design/coding, low power design, and timing/power/performance analysis
• Experienced with Synthesis, STA, PnR, DFT and ATPG, extraction, etc.
• Experience with pre-silicon RTL design verification, System Verilog or UVM/OVM/VMM, test bench creation, System Verilog Assertion (SVA)
• Adept with VHDL, Verilog, C/C++, and various scripting languages
• Strong written and verbal communication skills
• Experience in leading junior digital designers

Preferred qualifications:

• Solid understanding of UVM and formal verification methodologies
• Understanding and awareness of basic analog design
• Full command of Cadence design environment and Synopsis development tools