Physical Design Engineer (Co-Op) United States - Cisco Systems, Inc.

Applications are accepted until further notice. 

Please note this posting is to advertise potential job opportunities.This exact role may not be open today but could open in the near future.When you apply, a Cisco representative may contact you directly if a relevant position opens. 

Who You'll Work With 

Cisco is well known for developing ground-breaking products inshort timeintervals. To support new product development at an exciting pace the Acacia PD team is challenged to design, develop, and build ASIC designs. 

The work is essential for supporting the increasing demands of hybrid work environments and ensuring reliable, high-capacity network connections. 

The engineers work with technologies that involve the latest submicron technologies. An ASIC PD engineer would be involved in developing andoptimizingphysical floorplan and their implementation. 

What You'll Do 

The Physical Design Engineer Co-op will perform one or more of the following tasks while working on Cisco's elite optical communication products. The Co-op will be assigned relevant work assignments to challenge them according to their current level of experience and capability. 

The Co-op may find themselves working in the following areas: 

• Work with Front-End teams to understand the design architecture to ensureoptimalphysical implementation 
• Gate level netlist synthesis (physical synthesis) 
• Physical implementation (floorplanning, placement, CTS, routing) 
• Power,performanceand area optimization of design 
• Static Timing analysis and signoff closure 
• Physical verification and signoff closure 
• EMIR analysis and signoff closure 

Who You Are 

• Good interpersonal and organizational skills 
• Passionate about engineering and enjoy working with hardware AND software 
• Likes to be challenged to understand systems and figure out ways to break it 
• Automation and programming minded 
• Self-motivated, able to work independently whenrequired 
• Collaborative and team-focused with thestrong desireto learn and grow 
• Excellent English verbal and written communication skills 

Minimum Qualifications 

• Currently enrolled in a full-time undergraduate program in computer science, electrical engineering, or related program 
• Must be able to be onsite in Maynard, MA two days a week 
• Knowledge of the design cycle from RTL to GDSII 
• Understanding of Static Timing Analysis, timing closure and design constraints 
• Knowledge in block level synthesis, place and route, timing closure,PnRand signoff tools and their capabilities 

Preferred Qualifications 

• Interest in VLSI design, and more specifically in ASIC physical design and verification 
• Interest and preferably academic experience in deep submicron CMOS technologies 
• Scripting experience withperl,tcl, python and/or shell, a plus 
• Analytical and creative, with well-developed and tenacious problem-solving skills 
• Previousinternship experience 

Why Cisco 

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. 

We embrace digital, and help our customers implementchangein their digital businesses. Some may thinkwe’re“old” (40 years strong) and only about hardware, butwe’realso a software company. And a security company. We even invented an intuitive network that adapts, predicts,learnsand protects. No other company can do what we do – youcan’tput us in a box! 

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)