Packaging Signal/Power Integrity Engineer - Google

Sunnyvale, CA

About the Job

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practicalexperience.
4 years of experience in chip package SI/PI design for interconnections and advanced package design.
Experience in post silicon bring up or model correlation.

Preferred qualifications:

Experience in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, high speed SerDes, PCIex).
Experience in programming and data analysis in Matlab, Python, C++ to establish automation flows and data processing.
Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
Experience with chip top design, physical design, STA, package, system, validation teams.
Familiarity with memory testing, next generation memory and chiplet standards and timing budget methodology, including SI/PI co-analysis/design and channel design optimization.
Understanding of Static Timing Analysis (STA) and voltage budget.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level. You will be the part of a larger team with Chip Architects, ASIC Engineers, Physical Design and other SI/PI Engineers. You will work with various cross-functional teams, including Chip Design, System Design, software team and vendors. You will drive chip packaging signal and power implementations from product planning to New Product Introduction (NPI).

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Contribute to chip package system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists for High Performance Computing (HPC) based on 2.5D/3D package technology.
Develop the next generation memory interface considering input/output physical layer, SI/PI and physical design and interface IP evaluation.
Collaborate with chip design, system design teams and suppliers to drive chip package SI/PI design goal, define boundaries of chip design and explore SI/PI and Design for Manufacturing (DFM) trade-off for package design closure for production.
Provide feedback on chip floorplan considering package/system routability and Signal Integrity (SI)/Power Integrity (PI).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Source : Google