Hardware Engineering and R&D - Hardware Design Engineer 5 Hardware Design Engineer 5 - HireTalent
Mountain View, CA 94043-0000
About the Job
Job Title: Hardware Engineering and R&D - Hardware Design Engineer 5
Job Location: Mountain View, CA
Job Duration: 3 Months on W2 (Hybrid)
Job Description:
" A Silicon Design Verification Engineer with following qualifications
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related degree.
8+ years of experience working on ASIC design, verification, or related work experience.
Strong knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM
Define, document, ad implement a UVM verification environment including agents and scoreboards.
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
Setup and drive regression health through triage, coverage analysis, and advanced simulation debug techniques
Experience in pre- and post-silicon verification test flow and automated test benches
Support post-silicon verification activities of the products working with design, product teams.
Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
" Familiar with verification of IP's including
High Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs
Analog and Mixed-signal IP's such as Client's, Bandgaps, Power Regulators
uController (such as ARM, RISCV) based designs
DSPs
" Familiar with verification for testchips and tradeoffs of verifying IP vs SoC vs testchip
" Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
" Familiarity with Gate-level simulation (GLS) flows and SDF annotations is a plus
" Familiarity with AMS/MSV simulations and environments is a plus
Top 3 Hard Skills Required + Years of Experience
" Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM (5+ YOE)
" Experience with high Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs (5+ YOE)
" Analog and Mixed-signal IP's such as Client's, Bandgaps, Power Regulators (5+ YOE)
" Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes (5+ YOE)
Job Location: Mountain View, CA
Job Duration: 3 Months on W2 (Hybrid)
Job Description:
" A Silicon Design Verification Engineer with following qualifications
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related degree.
8+ years of experience working on ASIC design, verification, or related work experience.
Strong knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM
Define, document, ad implement a UVM verification environment including agents and scoreboards.
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
Setup and drive regression health through triage, coverage analysis, and advanced simulation debug techniques
Experience in pre- and post-silicon verification test flow and automated test benches
Support post-silicon verification activities of the products working with design, product teams.
Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
" Familiar with verification of IP's including
High Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs
Analog and Mixed-signal IP's such as Client's, Bandgaps, Power Regulators
uController (such as ARM, RISCV) based designs
DSPs
" Familiar with verification for testchips and tradeoffs of verifying IP vs SoC vs testchip
" Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
" Familiarity with Gate-level simulation (GLS) flows and SDF annotations is a plus
" Familiarity with AMS/MSV simulations and environments is a plus
Top 3 Hard Skills Required + Years of Experience
" Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM (5+ YOE)
" Experience with high Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs (5+ YOE)
" Analog and Mixed-signal IP's such as Client's, Bandgaps, Power Regulators (5+ YOE)
" Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes (5+ YOE)
Source : HireTalent