FPGA Design/Verification Engineer at Donatech Corporation
Orlando, FL
About the Job
Position would require the candidate to be a W2 employee of Donatech.
US Citizenship Required.
Develops, designs, verifies, and documents Field Programmable Gate Arrays (FPGA) development.
Determines architecture design, logic design, and system simulation.
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization.
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.
Support Circuit card designer with trade studies.
Develop and release design requirement specifications for product.
Support of production environment in debugging and troubleshooting FPGA related issues in a production environment will be a critical component of this particular role.
Required Experience:
Strong understanding and experience in FPGA design and verification is a requirement.
Candidate must be familiar with UVM and system verilog. High Level Synthesis (HLS) design experience is a plus.
Candidate must have experience integrating FPGA solution on hardware and design validation including simulation validation.
Active Secret Clearance is preferred. Candidates must have ability to obtain Interim Secret Clearance.
US Citizenship Required.
Develops, designs, verifies, and documents Field Programmable Gate Arrays (FPGA) development.
Determines architecture design, logic design, and system simulation.
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization.
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.
Support Circuit card designer with trade studies.
Develop and release design requirement specifications for product.
Support of production environment in debugging and troubleshooting FPGA related issues in a production environment will be a critical component of this particular role.
Required Experience:
Strong understanding and experience in FPGA design and verification is a requirement.
Candidate must be familiar with UVM and system verilog. High Level Synthesis (HLS) design experience is a plus.
Candidate must have experience integrating FPGA solution on hardware and design validation including simulation validation.
Active Secret Clearance is preferred. Candidates must have ability to obtain Interim Secret Clearance.