FPGA Design/Verification Engineer at Softworld Inc

***Due to the nature of the work being performed US Citizenship is required***

Job Title: FPGA Design/Verification Engineer

Location: Littleton Colorado 80125

Onsite Requirements:

• UVM
• Systems Verilog
• ASIC/FPGA

Job Description:

• Join us as an ASIC & FPGA Verification Engineer. You will have the opportunity to support over 50 different programs and research and development (R&D) efforts.
• Your work will affect technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions.

Daily Functions:

• Work with low SWaP, radiation hardened, space rated devices.
• Devise a unique verification plan for a given design.
• Use System Verilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
• Develop requirements, test cases, build test benches, generate reports, and document verification results.
• Work with an independent design team to document and resolve bugs found in the design.
• Support all aspects of ASIC and FPGA development, to include architecture, design, and analysis.
• Support technical reviews and be able to present to internal and external stakeholders.

Requirements:

• Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
• Experience in the design of FPGA and/or ASIC devices.
• HDL programming experience with VHDL, Verilog, and/or System Verilog.
• US Citizenship is required for this position.
• Experience in the verification of FPGA and/or ASIC devices.
• Experience with modern verification methodologies such as UVM/OVM.
• Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
• Experienced in scripting such as Perl, TCL, Python.
• Experience developing test cases based off given requirements.
• Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
• Experience identifying and implementing necessary test exclusions.
• Experience generating coverage reports (code and functional)
• Knowledge of space-grade/qualified FPGAs and ASICs.
• FPGA/ASIC design experience is a plus.