Field Programmable Gate Array Design Engineer - General Dynamics Land Systems US

The Field Programmable Gate Array (FPGA) Design Engineer position is responsible for electronics and FPGA design, implementation in support of video and image processing.

Company Information: 

General Dynamics is a successful Fortune 100, global aerospace and defense company, with over 90,000 employees world-wide. General Dynamics Land Systems, a business unit of General Dynamics, has a strong foundation of delivering core engineering and manufacturing capabilities to our clients for military vehicles. Our team is focused on continuous process and productivity improvements that reduce product costs, while increasing troop safety and effectiveness.  Land Systems continues to work with the US Armed Forces and its Allies to ensure these vehicles remain survivable, relevant, flexible, affordable and capable of addressing a dynamic threat environment.


Hybrid or onsite:

Hybrid is available but onsite presence will be required for up to 80% per week


What We Offer:
Starting your career or you are an experience professional, we offer a Total Rewards package that is Impactful and built for you. 

• Healthcare including medical, dental, vision, HSA and Flex Spending
• competitive base pay, incentive pay that rewards individual and team performance, and comprehensive benefits.
• 401k Match (6%)
• Educational Assistance
• 9-80 Work Schedule (This position’s standard work schedule is a 9/80. The 9/80 schedule allows employees who work a nine-hour day Monday through Thursday to take every other Friday off.)
• On-going learning opportunities within a diverse, inclusive and rewarding work environment
• Onsite Cafeteria, Fitness Center, and Outdoor fitness track

Tasks and Responsibilities: 

• Collaborating with systems, software, and hardware engineers to develop FPGA designs for video processing, control systems, and system interfaces
• Support existing and/or legacy FPGA designs
• Develop and review requirements and digest into work packages
• Collaborate with teams through issue tracking and use of revision control systems
• Implement designs using existing IP blocks from Xilinx and other third-party vendors
• Create new IP in VHDL, Verilog or HLS (C/C++)
• Develop system constraints and perform timing closure
• Perform debug through simulation and physical lab testing
• Develop embedded software for bare metal, real-time operating system (RTOS), and with Linux environment

Position Requirements:
 

• Bachelor's degree (B.A. or B.S.) in Electrical or Computer Engineering or Computer Science
• 10+ years of experience
• Experience with Git or similar revision control systems
• Experience with Jira or similar issue tracking systems
• Experience with designing ARM processors and AXI bus with Zynq Ultrascale+ MPSoC or understanding similar SoC FPGA architectures, including the PS-PL interfacing, either on bare-C or OS based designs
• Experience with industry-standard protocols, such as PCIe, USB, Ethernet, DDR, I2C, SPI, CAN, etc.
• Experience with generic video and camera interfaces such as LVDS, HDMI, Display Port, Camera Link, SDI, GigEVision, etc.
• Experience with Xilinx tool chain; Vivado, SDK, Vitis
• Experience writing RTOS and Linux device drivers for embedded systems

Pay Transparency:
GDLS considers factors such as scope/responsibilities of the position, candidate experience, and education/training background, in addition to local market comparable and business considerations, when extending an offer.