Silicon Design Engineer - Hybrid at Viva USA Inc.

Title: Silicon Design Engineer - Hybrid

Description:

THE ROLE:

The client is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

RTL design for memory I/O
PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
PHY link layer design, implementation & verification with Analog and System architect.
PHY Analog/Digital co-design
Digital design and RTL coding
Timing Synthesis & Drive Physical implementation
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the unit tests
Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

5+ years of experience
Digital design engineering experience
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
Knowledge of clocking architectures, synchronization, and CDC methodology
SERDES, DDR, Memory Controller, or MAC Design experience is preferred
Strong understanding of computer organization/architecture.
Mixed signal RTL experience is a plus
Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Note:
(Hybrid - 3 days a week)

Mandatory skills:

RTL design, RTL coding,
PHY Digital Architecture development, pathfinding, coding, verification,
PHY link layer design, implementation, verification, PHY Analog, Digital co-design,
Linux, Windows, Verilog, System Verilog, C, C++,
computer organization, computer architecture,
unit test, test issues, UVM testbenches,
Digital design, hardware, firmware, Digital design engineering, System Verilog Assertions,
clocking architectures, synchronization, CDC methodology, SERDES, DDR, Memory Controller, MAC Design

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008