Design Verification Engineer - Meta

Summary:

We are growing our silicon design engineering team to support research silicon development for RL Research (RL-R) teams. We build small scale research silicon to demonstrate and integrate advanced IP into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP and fabrication techniques, to prove advanced architectures and to harden controls/algorithms for next generation AR/VR silicon solutions in support of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, reviewing and executing our front-end verification efforts at the IP and sub-system levels. You will collaborate in improving DV methodologies and establishing best practices. Your expertise is needed in all phases of the chip development from DV planning to Gate Level Simulations and final sign off. Collaboration with other DVE is paramount for understanding the DV strategy and plan and executing on the same page and mindset. Our team is developing and implementing the next generation custom and semi-custom digital SOC’s/ASIC’s to drive our industry leading virtual and augmented reality systems.

Required Skills:

Design Verification Engineer Responsibilities:

1. Self sufficient and detail oriented in all phases of Design Verification from IP to SoC level.

2. Provide feedback on IP/sub-system micro-architecture and RTL design.

3. Provide feedback on DV methodology, strategy and test planning.

4. Support earlier FW development with development bare metal drivers.

5. Help create and maintain design documentation including IP/SoC Verification Architecture document (collaborator/owner), IP/SoC Design Verification plan (collaborator) and SoC/chip bringup/validation plan (collaborator).

6. Contribute to DV efforts at block, subsystem and SoC level.

Minimum Qualifications:

Minimum Qualifications:

7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

8. 3+ years of experience as a Design Verification Engineer.

9. Proven communication and collaboration skills.

10. Knowledge of digital verification (SystemVerilog, UVM) and embedded firmware (C).

11. Proven debug experience.

12. Experience in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs.

13. Experience with vendor VIPs, integration and troubleshooting.

Preferred Qualifications:

Preferred Qualifications:

14. Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc.

15. Experience with Gate Level Sims (GLS).

16. Python (or similar) scripting experience.

17. Experience with embedded C FW/SW development for pre-silicon verification and post-silicon bringup.

18. Master’s degree in Electrical Engineer or Computer Engineer.

Public Compensation:

$136,000/year to $203,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.