Design verification engineer at Tek Labs Inc

DV Responsibilities

• Manage complex subsystem verification with Synopsys peripherals- testbench development, coverage and validation and should be able to hit the ground running in Cadence flows
• Need to be able to handle Auto qualification needs
• Cadence design flow and Synopsys IP peripherals
• 8 to 12++ years with good communication and should independently work with the logic team and other functions to drive the tasks.