Design Engineer-Full Chip leve-Minimum 8 years Required - Mega Cloud Lab

Role : Design Engineer

Location : Santa Clara, CA (Onsite)

Longterm Contract

·& & &

& & & & & 8-10 years of design experience in developing synthesis constraint at module and Full Chip level

·& & & & & & & & Experience in promoting subsystem level RDC/CDC constraint to SoC Top

·& & & & & & & & Experience in debugging and triaging Lint CDC/RDC errors or issues

·& & & & & & & & Experience in converting spyglass constraints to realintent constraints

·& & & & & & & & Experience in creating lint RDC/CDC constraints both at IP level , Fullchip or Top level

·& & & & & & & & Experience in promoting IP level or SoC Constraints



& & 8-10 years of design experience in developing synthesis constraint at module and Full Chip level

·& & & & & & & & Experience in promoting subsystem level RDC/CDC constraint to SoC Top

·& & & & & & & & Experience in debugging and triaging Lint CDC/RDC errors or issues

·& & & & & & & & Experience in converting spyglass constraints to realintent constraints

·& & & & & & & & Experience in creating lint RDC/CDC constraints both at IP level , Fullchip or Top level

·& & & & & & & & Experience in promoting IP level or SoC Constraints