Design Engineer, Custom Circuits - Google

Minimum qualifications:

• Masters degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
• 3 years of experience in technical circuit and physical design field.
• Experience in transistor level design in advanced finfet technology nodes (i.e. SPICE simulations or concurrent optimization across custom circuit/IP and physical design spaces.

Preferred qualifications:

• Experience delivering optimized custom circuits/memories/IPs and digital blocks leading to product tapeout.
• Experience with programming/scripting (Python, TCL).
• Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
• Understanding of design kit collaterals for front end and back end design teams.
• Familiarity with industry standard tools for synthesis, place and route, and static timing analysis.

About the job

As a Design Engineer, Custom Circuits you will collaborate with circuit design, physical design, technology, and hardware architecture leads to overcome the slowing of Moore’s Law and deliver cutting edge ASIC’s and SoC’s. You will work on topics that span circuit design, memories, digital block optimization, clock distribution, floorplanning, third party IPs, and foundry engagement. You will drive new and novel methodologies that co-optimize across the entire design space, and see these through from inception to maturity and tapeout. As a part of this work, you will participate in the development of exceptional technology in high performance computing and file associated patents.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Googles product portfolio possible. Were proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. 

Responsibilities

• Work with our foundry and IP partners, our Technology, Physical Design, and Architecture teams in advanced CMOS nodes.
• Analyze and implement SRAMs and other memories, build and simulate custom circuits, and support test chip design/execution/validation.
• Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
• Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.