Job Details:

Job Description: 

About the Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Foundry Technology Development (TD) is the heart and soul of Moore's Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD's more than 10,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. You will be a key member of the Design Enablement customer application and support team and will own significant customer enablement tasks in a fast-paced and technically challenging environment. TD is working on development of the best-in-class technology platform for the Foundry customers. Our organization is responsible for enabling the FIP segment of the platform, focusing on embedded custom memories, memory compilers, standard cell libraries and analog and mixed signal foundational IPs. As a technical leader in the Foundational IP (FIP) Enablement and Support team, you will be responsible for building, evolving and managing the Design Automation DevOps functions while leading and developing management skills or managers with relevant hands-on experience.

We are looking to establish crucial development and deployment capabilities for our team in:

- Cross-platform QA and delivery of applications improving FIP ease of use and customization.
- Integration QA workflows verifying compatibility with multiple EDA reference workflows in the SoC design context.
- Streamlining of the FIP platform specification development and change control, and QA integration.
- Support and development process integration in tools like GitHub, Jira Software and Jira Service Management.

You will be responsible for but not limited to:

- Architecting design automation solution, contributing to implementation, leveraging industry standard DevOps tools and methods for CI/CD and applications delivery.
- Collaborate with the org leadership and Technical Program Management on the design automation roadmap definition, prioritization, effort and scheduling estimates.
- Apply your leadership experience to coach and upskill design automation team members and collaborate closely with SoC design and IP QA experts on streamlining and scaling of the FIP Integration QA solutions.

#Design Enablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate will possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineer or Computer Engineering or related STEM field.

In addition to minimum degree and experience, you will have 8+ years of relevant experience in:

• Leading design and workflow automation efforts in SoC design, EDA, or IP development domains.

• Applying industry standard DevOps practices, including integration of workflows around GitHub and Jira.

• Leverage Industry standard tools and methods for CI/CD, application delivery, containerization.

• Experience working within cross-functional teams, customers, suppliers and with Technical Program Management.

• Establishing process improvements.

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Preferred Qualifications:

• EDA solutions experience on the cloud.

• Knowledge of FIP ecosystem and standard engineering practices.

• Customer orientation and experience with prioritizing issues and tasks.

• Track record of building organizations and evolving design automation and DevOps capabilities in one or more of the following domains: DTCO, SoC, ASIC, IP or FIP design, Application Support Engineering.

• Background and experience in project management systems using Agile, Waterfall, etc. practices.

• Soc design methodology, FIP, IC manufacturing and process technology knowledge.

• Jira Software and Jira Service Management experience.

• Foundry or EDA industry background or experience.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$162,228.00-$243,284.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.