CPU Timing Convergence Lead, Physical Design, Silicon - Google
Mountain View, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with Static Timing Analysis.
- Experience in high speed design timing convergence and in STA tools like Primetime or Tempus.
Preferred qualifications:
- Experience and understanding in engineering across timing analysis and design implementation.
- Experience in the delivery of high performance silicon in latest technology process nodes.
- Experience in extraction of design parameters, QoR metrics and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
- Understanding of Static Timing Analysis including sign-off corner definitions, process margining, interface timing constraints, high frequency timing convergence and setting up of frequency goals with technology scaling and PDK changes.
- Strong scripting and data mining skills.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Drive the sign-off timing convergence for high performance designs. Responsibilities include setting up the timing constraints, defining the overall STA methodology, STA infrastructure and sign-off convergence flows and working closely with stakeholders throughout the project for sign-off timing convergence.
- Collaborate with the RTL design teams on microarchitectural critical items for timing and power convergence.
- Drive or develop physical design timing convergence tools and flows for advanced CPU designs to achieve outstanding Power Performance Area (PPA).