CPU RTL Design Manager, Silicon - Google
Mountain View, CA
About the Job
Note: Google’s hybrid workplace includes remote and in-office roles. By applying to this position you will have an opportunity to share your preferred working location from the following:In-office locations: Mountain View, CA, USA; Austin, TX, USA; Poughkeepsie, NY, USA.Remote location(s): Oregon, USA.Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in high-performance CPU or AI accelerator logic/RTL design including micro-architecture definition and PPA optimizations.
- 6 years of experience in people management, developing employees.
- Experience with HDL language and front-end design methodology.
- Experience with CPU or AI accelerator integration with SoC.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with SoC design, architect, and integration.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will contribute to all phases of designs of Central Processing Unit (CPU) subsystems from design specification to productization, including integration into goal System on a chips (SoC).
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Develop CPU subsystem front-end designs, emphasizing micro-architecture and RTL design for the next generation CPU.
- Propose performance enhancing micro-architecture features, and work with Software, Architect, and Performance teams for trade-off studies.
- Deliver designs meeting Performance, Power, Area (PPA) goals with production quality and become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
Source : Google