Chassis Power Architect, Silicon - Google

Mountain View, CA

About the Job

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
6 years of experience in power optimization workflow.
Experience with silicon power optimization methods and techniques.
Experience with power management IPs.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in post-silicon power calibrations and debug.
Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
Experience in using Electronic Design Automation (EDA) tools, such as Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
Experience in design and analysis of full chip power, with an understanding of clock, reset, and power sequencing interactions.
Understanding of ASIC design flows and methodology.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

As part of the Google Silicon Platform IP team, you will collaborate with hardware architects and design engineers to drive chassis power optimization in advanced technology nodes, focused on Google Tensor SoC and other associated products.

In this role, you will define power optimization methods, chart power roadmaps for chassis IPs, propose power optimization plans in consultation with cross-functional teams, guide pre-silicon power modeling and post-silicon power correlation efforts, and interface with system and chipset power architects on both power planning and power management strategies. You will focus on our next-generation chassis power architecture, microarchitecture, and power versus performance trade-offs.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Drive power methodology for design, verification, and implementation of deep submicron SoCs.
Develop innovative schemes to achieve power optimization from circuit to system level.
Influence generic power management IPs to drive clock, reset, and power controls.
Plan the methodologies for achieving power reduction. Work with tool vendors to address any power-related tool or flow issues.
Work with architects, logic, circuit, and physical designers to understand the power requirements and define all power budgets and roadmaps.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Source : Google