ASIC RTL Design Engineer - Google

Sunnyvale, CA

About the Job

Minimum qualifications:

Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
Experience with Logic Design.

Preferred qualifications:

Experience interacting with software, architecture, and other cross-functional teams.
Experience applying computer architecture principles to solve open-ended problems.
Experience in working with switching, buffering, queueing, and scheduling.

About the job

Google Engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people.

As a member of the Digital Design team, you'll work to craft the architecture for the current and future ASIC projects, and work with the verification and validation teams to ensure proper testing of features. You will work closely with the Google product teams to ensure their goals are met with your microarchitecture designs. You will also work with physical design and manufacturing teams to ensure that your designs are viable.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Help define the architecture and microarchitecture of current and future generations of ASIC.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with Design Verification teams to create testplans to verify and debug design RTL.
Work with Physical Design teams to ensure design meets physical requirements and timing closure.
Work closely with software teams to ensure end-to-end solutions.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Source : Google