ASIC RTL Design Engineer, Machine Learning Accelerators - Google
Sunnyvale, CA
About the Job
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Digital design experience using SystemVerilog RTL
Preferred qualifications:
- 3 years of experience in digital design using SystemVerilog or RTL.
- Experience with high-bandwidth bus architectures including control and memory bus architectures, die-to-die interconnects, or inter-chip interconnects.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience defining SoC IP interfaces and methodologies.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
- Work with design validation (DV) teams to create testplans for, verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.