ASIC/FPGA Design Verification Engineer with UVM Experience at The Fountain Group

The Fountain Group is currently seeking an ASIC/FPGA Design Verification Engineer for a prominent client of ours. This position is located in El Segundo, CA. Details for the position are as follows:
 
Payrate: $66/hr W2
 
Job Title: ASIC/FPGA Design Verification Engineer with UVM Experience
Location: El Segundo, CA
Duration: 6 months contract.
 
Shift: 7am to 4pm.
 
Job Description:
Create UVM simulation plan from design specification.
Create or modify UVC, Score Board, Monitor, and test cases.
Verify until functional coverage and code coverage meet project threshold.
Document results.
 
Required Skills:

• U. S CITIZEN REQUIRED (NO DUAL CITIZENSHIP)
• Bachelors degree
• 5+ years of experience
• 1-2 years of UVM tool
• Cadence Xcelium verification tool

 
UVM Experience (Universal Verification Methodology (UVM) verification is a standardized form of design verification used in FPGA and ASIC design projects.)
 
If you are interested in hearing more about the position please respond to this posting with your resume attached or contact me at 813 444 5839.

Please forward this email to any friends or colleagues as we do offer a Referral Bonus for any candidate who is hired and still gainfully employed after 30 days.