ASIC/FPGA Design Verification Engineer - US Tech Solutions, Inc.
El Segundo, CA 90245-3507
About the Job
Job Title: ASIC/FPGA Design Verification Engineer
Location: El Segundo, CA
Duration: 6 Months
Job Description
Location: El Segundo, CA
Duration: 6 Months
Job Description
- Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
- ASIC/FPGA Design Verification Engineer with UVM Experience
- 5+ years of experience
- 1-2 years of UVM tool
- Cadence Xcelium verification tool
- Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Source : US Tech Solutions, Inc.