Asic Engineer Intern, Custom Compression IPs on Next Gen AR Glasses - Meta
Sunnyvale, CA
About the Job
Our team, within Reality Labs at Meta, is dedicated to implementing hardware accelerators for compression algorithms. These accelerators are crucial for our Graphics Rendering Engine and Display Reprojection Pipeline, helping us adhere to stringent power and area constraints. We are pioneering advancements in personal computing and challenging conventional industry beliefs about the potential of smart wearable technology, with a focus on developing the next generation of AR glasses.We are looking for upcoming engineers who have interest in custom RTL development and hardware acceleration. This role is essential to realizing our vision for AR glasses, ensuring the meet performance, power, and form-factor coming from the system level requirements.We are looking for individuals with experience in various stages of the silicon lifecycle to help build and scale silicon for our smart wearables products. As an ASIC Engineer in our team, you will join a dynamic group of industry leaders, working on the development and support of innovative ASIC solutions for Meta’s Reality Labs products.Our internships are twelve (12) to sixteen (16) weeks long.
RESPONSIBILITIES
Asic Engineer Intern, Custom Compression IPs on Next Gen AR Glasses Responsibilities:
MINIMUM QUALIFICATIONS
Minimum Qualifications:
PREFERRED QUALIFICATIONS
Preferred Qualifications:
RESPONSIBILITIES
Asic Engineer Intern, Custom Compression IPs on Next Gen AR Glasses Responsibilities:
- RTL development using SystemVerilog.
- Participate in Micro-architecture, Design, and Verification reviews and provide feedback.
- Analyze design and enhance PPA (Power, Performance, Area).
- Support Verification to analyze and improve Verification Coverage.
- Debug simulations.
MINIMUM QUALIFICATIONS
Minimum Qualifications:
- Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
- Knowledge of VHDL, Verilog or SystemVerilog.
- Knowledge of Logic Design Fundamentals.
- Must obtain work authorization in the country of employment at the time of hire, and maintain on-going work authorization during employment.
PREFERRED QUALIFICATIONS
Preferred Qualifications:
- Experience with Lint, Synthesis, Timing Closure, Formal Verification or Physical Design tools.
- Experience with scripting languages (Python, Perl, TCL, shell scripting)
- Experience with AR/VR technologies, Compression, Image Processing.
- Experience in data path development.
- Demonstrated experience via an internship, work experience, coding competitions, or widely used contributions in open source repositories (e.g. GitHub).
- Intent to return to degree-program after the completion of the internship/co-op.
Source : Meta