ASIC Design for Test - Technical Lead at CISCO Systems
San Diego, CA 92101
About the Job
The application window is expected to close on 10/15/2024This is an onsite role and will require working out of the Milpitas/San Jose office location.Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products
We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world
Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio
Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test
You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
As a member of this team you will also be involved in crafting groundbreaking next generation networking chips
You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.Your team will participate in the creation of Innovative Hardware DFT & Test timing analysis for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship
Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 7 years of experience. Prior experience with Jtag protocols ( p1500, p1687) , Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development – Test Architecture, Methodology and Infrastructure Why Cisco#WeAreCisco - We connect everything: people, processes, data, and things
We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals
And we do it in style with unique personalities who aren't afraid to change the way the world works, lives, plays and learns.We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars
We celebrate the creativity and diversity that fuels our innovation
We are dreamers and we are doers.Location:San Diego, California, USArea of InterestEngineer - HardwareCompensation Range146000 USD - 205400 USD Job TypeProfessionalTechnology InterestNetworkingJob Id1427343Message to applicants applying to work in the U.S
and/or Canada:When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S
and/or Canada locations, not including equity or benefits
For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses
Hiring ranges for sales positions include base and incentive compensation target
Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training
Applicants may not be eligible for the full salary range based on their U.S
or Canada hiring location
The recruiter can share more details about compensation for the role in your location during the hiring process.U.S
employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings
Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday
Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO
We offer additional paid time to volunteer and give back to the community
Employees are also able to purchase company stock through our Employee Stock Purchase Program.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components
For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target
Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world
Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio
Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test
You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
As a member of this team you will also be involved in crafting groundbreaking next generation networking chips
You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.Your team will participate in the creation of Innovative Hardware DFT & Test timing analysis for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship
Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 7 years of experience. Prior experience with Jtag protocols ( p1500, p1687) , Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development – Test Architecture, Methodology and Infrastructure Why Cisco#WeAreCisco - We connect everything: people, processes, data, and things
We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals
And we do it in style with unique personalities who aren't afraid to change the way the world works, lives, plays and learns.We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars
We celebrate the creativity and diversity that fuels our innovation
We are dreamers and we are doers.Location:San Diego, California, USArea of InterestEngineer - HardwareCompensation Range146000 USD - 205400 USD Job TypeProfessionalTechnology InterestNetworkingJob Id1427343Message to applicants applying to work in the U.S
and/or Canada:When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S
and/or Canada locations, not including equity or benefits
For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses
Hiring ranges for sales positions include base and incentive compensation target
Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training
Applicants may not be eligible for the full salary range based on their U.S
or Canada hiring location
The recruiter can share more details about compensation for the role in your location during the hiring process.U.S
employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings
Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday
Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO
We offer additional paid time to volunteer and give back to the community
Employees are also able to purchase company stock through our Employee Stock Purchase Program.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components
For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target
Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.