ASIC Design Engineer, Platform IP, Silicon - Google

Minimum qualifications:

1. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
3. Experience with logic synthesis techniques to improve RTL code, performance, and power as well as low-power design techniques.
4. Experience with ARM-based SoCs, interconnects, and ASIC methodology.
5. Experience with a scripting language like Python or Perl.

Preferred qualifications:

1. Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
2. 3 years of experience with Intellectual Property (IP) design for clocking, interconnects or peripherals.
3. Experience with methodologies for low power estimation, timing closure, or synthesis.
4. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our team takes pride in our ability to transform algorithms and processes into a user-friendly form. If you are someone who enjoys crafting tools to empower other creative people then this is the right job for you. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google https://careers.google.com/benefits/

Responsibilities:

1. Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
2. Perform RTL development (SystemVerilog), debug functional/performance simulations.
3. Perform RTL quality checks including Lint, Critical Dimension Control, Synthesis, Unified Power Format checks.
4. Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
5. Communicate and work with multi-disciplined and multi-site teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf. If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2

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