Requires a Bachelorâ€™s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience.
CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is preferred at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.Responsibilities for this Position:
The Senior Advanced ASIC Engineer will be responsible for front-end ASIC Design including synthesis, timing analysis, test insertion, and manufacturing test development. Successful candidates will have a thorough understanding of synchronous digital design concepts and have prior experience with ASIC development process. Must be knowledgeable in Verilog RTL coding and be proficient in synthesis, static timing analysis, SDC constraints, and formal equivalency checking. Should be able to generate manufacturing test vectors and manufacturing test plan. Knowledge of scan/MBIST insertion and ATPG is a plus. Must have strong written and oral communication skills.
In addition, the successful candidate must be able to effectively and efficiently work with other team members to include other IC design and verification engineers, systems engineers, software engineers, project managers, customers and tool suppliers.
Basic Qualifications for a Senior Advanced ASIC Engineer
- Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with technical MS, 4 years with technical PhD)
- Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
- Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
- Experience with the current ASIC design tools for all phases described above
- Simulation â€“ Mentor QuestaSim
- Synthesis â€“ Synopsys Design Compiler
- Static Timing â€“ Synopsys Primetime
- Logic Equivalency Checking â€“ Synopsys Formality
- DFT Insertion â€“ Synopsys DFTMax and Mentor Graphics Tessent
- Manufacturing Test Development â€“ Synopsys TetraMax
- SDC (Synopsys Design Constraints)
- Must have completed tape-out of multiple ASIC designs
- Ability to obtain and hold a TS/SCI Security Clearance
- Experience with most, if not all, of the following languages are highly desired:
- Experience with chip level integration as ASIC chip lead
- Experience with RTL development and debug
- Strong design automation skills
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high performance team!
General Dynamics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce. EOE/Disability/Veteran